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<ul>
<li><a href="#about" style=" font-size: 16px;">Synthesis Messages</a></li>
<li><a href="#summary" style=" font-size: 16px;">Synthesis Details</a></li>
<li><a href="#resource" style=" font-size: 16px;">Resource</a>
<ul>
<li><a href="#usage" style=" font-size: 14px;">Resource Usage Summary</a></li>
<li><a href="#utilization" style=" font-size: 14px;">Resource Utilization Summary</a></li>
</ul>
</li>
<li><a href="#timing" style=" font-size: 16px;">Timing</a>
<ul>
<li><a href="#clock" style=" font-size: 14px;">Clock Summary</a></li>
<li><a href="#performance" style=" font-size: 14px;">Max Frequency Summary</a></li>
<li><a href="#detail timing" style=" font-size: 14px;">Detail Timing Paths Informations</a></li>
</ul>
</li>
</ul>
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<div id="content">
<h1><a name="about">Synthesis Messages</a></h1>
<table class="summary_table">
<tr>
<td class="label">Report Title</td>
<td>GowinSynthesis Report</td>
</tr>
<tr>
<td class="label">Design File</td>
<td>D:\GaoYun_pro\GW1NR_9C\src\IP\gowin_rpll\gowin_rpll.v<br>
D:\GaoYun_pro\GW1NR_9C\src\IP\gowin_sp\RAM.v<br>
D:\GaoYun_pro\GW1NR_9C\src\mem_mux.v<br>
D:\GaoYun_pro\GW1NR_9C\src\picorv32.v<br>
D:\GaoYun_pro\GW1NR_9C\src\psram.v<br>
D:\GaoYun_pro\GW1NR_9C\src\riscv32.v<br>
D:\GaoYun_pro\GW1NR_9C\src\riscv32_alu.v<br>
D:\GaoYun_pro\GW1NR_9C\src\spi.v<br>
D:\GaoYun_pro\GW1NR_9C\src\top.v<br>
D:\GaoYun_pro\GW1NR_9C\src\uart_debug.v<br>
D:\GaoYun_pro\GW1NR_9C\src\uart_memory.v<br>
D:\GaoYun_pro\GW1NR_9C\src\uart_recv.v<br>
D:\GaoYun_pro\GW1NR_9C\src\uart_txd.v<br>
D:\GaoYun_pro\GW1NR_9C\src\IP\gowin_clkdiv\gowin_clkdiv.v<br>
D:\GaoYun_pro\GW1NR_9C\src\vga_driver.v<br>
D:\GaoYun_pro\GW1NR_9C\src\hdmi\svo_defines.vh<br>
D:\GaoYun_pro\GW1NR_9C\src\hdmi\svo_hdmi_top.v<br>
D:\GaoYun_pro\GW1NR_9C\src\hdmi\svo_tmds.v<br>
</td>
</tr>
<tr>
<td class="label">GowinSynthesis Constraints File</td>
<td>---</td>
</tr>
<tr>
<td class="label">Version</td>
<td>GowinSynthesis V1.9.8.06-1</td>
</tr>
<tr>
<td class="label">Part Number</td>
<td>GW1NR-LV9QN88PC6/I5</td>
</tr>
<tr>
<td class="label">Device</td>
<td>GW1NR-9C</td>
</tr>
<tr>
<td class="label">Created Time</td>
<td>Tue Aug 08 11:03:52 2023
</td>
</tr>
<tr>
<td class="label">Legal Announcement</td>
<td>Copyright (C)2014-2022 Gowin Semiconductor Corporation. ALL rights reserved.</td>
</tr>
</table>
<h1><a name="summary">Synthesis Details</a></h1>
<table class="summary_table">
<tr>
<td class="label">Top Level Module</td>
<td>top</td>
</tr>
<tr>
<td class="label">Synthesis Process</td>
<td>Running parser:<br/>&nbsp;&nbsp;&nbsp;&nbsp;CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 261.555MB<br/>Running netlist conversion:<br/>&nbsp;&nbsp;&nbsp;&nbsp;CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB<br/>Running device independent optimization:<br/>&nbsp;&nbsp;&nbsp;&nbsp;Optimizing Phase 0: CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s, Peak memory usage = 261.555MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Optimizing Phase 1: CPU time = 0h 0m 0.468s, Elapsed time = 0h 0m 0.46s, Peak memory usage = 261.555MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Optimizing Phase 2: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 261.555MB<br/>Running inference:<br/>&nbsp;&nbsp;&nbsp;&nbsp;Inferring Phase 0: CPU time = 0h 0m 0.25s, Elapsed time = 0h 0m 0.232s, Peak memory usage = 261.555MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Inferring Phase 1: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.073s, Peak memory usage = 261.555MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Inferring Phase 2: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.079s, Peak memory usage = 261.555MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Inferring Phase 3: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.046s, Peak memory usage = 261.555MB<br/>Running technical mapping:<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 0: CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s, Peak memory usage = 261.555MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 1: CPU time = 0h 0m 0.406s, Elapsed time = 0h 0m 0.397s, Peak memory usage = 261.555MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 2: CPU time = 0h 0m 0.484s, Elapsed time = 0h 0m 0.49s, Peak memory usage = 261.555MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 3: CPU time = 0h 1m 6s, Elapsed time = 0h 1m 7s, Peak memory usage = 261.555MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 4: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 261.555MB<br/>Generate output files:<br/>&nbsp;&nbsp;&nbsp;&nbsp;CPU time = 0h 0m 0.593s, Elapsed time = 0h 0m 0.725s, Peak memory usage = 261.555MB<br/></td>
</tr>
<tr>
<td class="label">Total Time and Memory Usage</td>
<td>CPU time = 0h 1m 15s, Elapsed time = 0h 1m 16s, Peak memory usage = 261.555MB</td>
</tr>
</table>
<h1><a name="resource">Resource</a></h1>
<h2><a name="usage">Resource Usage Summary</a></h2>
<table class="summary_table">
<tr>
<td class="label"><b>Resource</b></td>
<td><b>Usage</b></td>
</tr>
<tr>
<td class="label"><b>I/O Port </b></td>
<td>43</td>
</tr>
<tr>
<td class="label"><b>I/O Buf </b></td>
<td>31</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspIBUF</td>
<td>6</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspOBUF</td>
<td>15</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspTBUF</td>
<td>6</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspELVDS_OBUF</td>
<td>4</td>
</tr>
<tr>
<td class="label"><b>Register </b></td>
<td>1275</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspDFF</td>
<td>67</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspDFFE</td>
<td>584</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspDFFSE</td>
<td>29</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspDFFR</td>
<td>121</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspDFFRE</td>
<td>228</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspDFFP</td>
<td>1</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspDFFPE</td>
<td>2</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspDFFC</td>
<td>98</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspDFFCE</td>
<td>144</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspDFFNE</td>
<td>1</td>
</tr>
<tr>
<td class="label"><b>LUT </b></td>
<td>4179</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspLUT2</td>
<td>280</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspLUT3</td>
<td>955</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspLUT4</td>
<td>2944</td>
</tr>
<tr>
<td class="label"><b>ALU </b></td>
<td>360</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspALU</td>
<td>360</td>
</tr>
<tr>
<td class="label"><b>INV </b></td>
<td>15</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspINV</td>
<td>15</td>
</tr>
<tr>
<td class="label"><b>IOLOGIC </b></td>
<td>3</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspOSER10</td>
<td>3</td>
</tr>
<tr>
<td class="label"><b>BSRAM </b></td>
<td>10</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspSP</td>
<td>8</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspSDPB</td>
<td>2</td>
</tr>
<tr>
<td class="label"><b>CLOCK </b></td>
<td>2</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspCLKDIV</td>
<td>1</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbsprPLL</td>
<td>1</td>
</tr>
</table>
<h2><a name="utilization">Resource Utilization Summary</a></h2>
<table class="summary_table">
<tr>
<td class="label"><b>Resource</b></td>
<td><b>Usage</b></td>
<td><b>Utilization</b></td>
</tr>
<tr>
<td class="label">Logic</td>
<td>4554(4194 LUTs, 360 ALUs) / 8640</td>
<td>53%</td>
</tr>
<tr>
<td class="label">Register</td>
<td>1275 / 6693</td>
<td>19%</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp--Register as Latch</td>
<td>0 / 6693</td>
<td>0%</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp--Register as FF</td>
<td>1275 / 6693</td>
<td>19%</td>
</tr>
<tr>
<td class="label">BSRAM</td>
<td>10 / 26</td>
<td>38%</td>
</tr>
</table>
<h1><a name="timing">Timing</a></h1>
<h2><a name="clock">Clock Summary:</a></h2>
<table class="summary_table">
<tr>
<th>Clock Name</th>
<th>Type</th>
<th>Period</th>
<th>Frequency(MHz)</th>
<th>Rise</th>
<th>Fall</th>
<th>Source</th>
<th>Master</th>
<th>Object</th>
</tr>
<tr>
<td>clk</td>
<td>Base</td>
<td>37.037</td>
<td>27.0</td>
<td>0.000</td>
<td>18.519</td>
<td> </td>
<td> </td>
<td>clk_ibuf/I </td>
</tr>
<tr>
<td>spi_clk_inter</td>
<td>Base</td>
<td>20.000</td>
<td>50.0</td>
<td>0.000</td>
<td>10.000</td>
<td> </td>
<td> </td>
<td>spi_u0/spi_clk_inter_s1/F </td>
</tr>
<tr>
<td>u_pll/rpll_inst/CLKOUT.default_gen_clk</td>
<td>Generated</td>
<td>7.937</td>
<td>126.0</td>
<td>0.000</td>
<td>3.968</td>
<td>clk_ibuf/I</td>
<td>clk</td>
<td>u_pll/rpll_inst/CLKOUT </td>
</tr>
<tr>
<td>u_pll/rpll_inst/CLKOUTP.default_gen_clk</td>
<td>Generated</td>
<td>7.937</td>
<td>126.0</td>
<td>0.000</td>
<td>3.968</td>
<td>clk_ibuf/I</td>
<td>clk</td>
<td>u_pll/rpll_inst/CLKOUTP </td>
</tr>
<tr>
<td>u_pll/rpll_inst/CLKOUTD.default_gen_clk</td>
<td>Generated</td>
<td>15.873</td>
<td>63.0</td>
<td>0.000</td>
<td>7.937</td>
<td>clk_ibuf/I</td>
<td>clk</td>
<td>u_pll/rpll_inst/CLKOUTD </td>
</tr>
<tr>
<td>u_pll/rpll_inst/CLKOUTD3.default_gen_clk</td>
<td>Generated</td>
<td>23.810</td>
<td>42.0</td>
<td>0.000</td>
<td>11.905</td>
<td>clk_ibuf/I</td>
<td>clk</td>
<td>u_pll/rpll_inst/CLKOUTD3 </td>
</tr>
<tr>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk</td>
<td>Generated</td>
<td>39.683</td>
<td>25.2</td>
<td>0.000</td>
<td>19.841</td>
<td>u_pll/rpll_inst/CLKOUT</td>
<td>u_pll/rpll_inst/CLKOUT.default_gen_clk</td>
<td>u_div_5/clkdiv_inst/CLKOUT </td>
</tr>
</table>
<h2><a name="performance">Max Frequency Summary:</a></h2>
<table class="summary_table">
<tr>
<th>No.</th>
<th>Clock Name</th>
<th>Constraint</th>
<th>Actual Fmax</th>
<th>Logic Level</th>
<th>Entity</th>
</tr>
<tr>
<td>1</td>
<td>spi_clk_inter</td>
<td>50.0(MHz)</td>
<td>237.0(MHz)</td>
<td>3</td>
<td>TOP</td>
</tr>
<tr>
<td>2</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk</td>
<td>25.2(MHz)</td>
<td>55.3(MHz)</td>
<td>13</td>
<td>TOP</td>
</tr>
</table>
<h2><a name="detail timing">Detail Timing Paths Information</a></h2>
<h3>Path&nbsp1</h3>
<b>Path Summary:</b></br>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-2.993</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>42.926</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>39.933</td>
</tr>
<tr>
<td class="label">From</td>
<td>spi_u0/spi_start_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>spi_u0/spi_clk_control_pos_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>spi_clk_inter[R]</td>
</tr>
</table>
<b>Data Arrival Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>39.683</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>40.046</td>
<td>0.363</td>
<td>tCL</td>
<td>RR</td>
<td>1271</td>
<td>u_div_5/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>40.409</td>
<td>0.363</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>spi_u0/spi_start_s1/CLK</td>
</tr>
<tr>
<td>40.867</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>10</td>
<td>spi_u0/spi_start_s1/Q</td>
</tr>
<tr>
<td>41.347</td>
<td>0.480</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>spi_u0/n94_s1/I1</td>
</tr>
<tr>
<td>42.446</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>spi_u0/n94_s1/F</td>
</tr>
<tr>
<td>42.926</td>
<td>0.480</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>spi_u0/spi_clk_control_pos_s1/D</td>
</tr>
</table>
<b>Data Required Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>spi_clk_inter</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>21</td>
<td>spi_u0/spi_clk_inter_s1/F</td>
</tr>
<tr>
<td>40.363</td>
<td>0.363</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>spi_u0/spi_clk_control_pos_s1/CLK</td>
</tr>
<tr>
<td>40.333</td>
<td>-0.030</td>
<td>tUnc</td>
<td> </td>
<td> </td>
<td>spi_u0/spi_clk_control_pos_s1</td>
</tr>
<tr>
<td>39.933</td>
<td>-0.400</td>
<td>tSu</td>
<td> </td>
<td>1</td>
<td>spi_u0/spi_clk_control_pos_s1</td>
</tr>
</table>
<b>Path Statistics:</b>
<table class="summary_table">
<tr>
<td class="label">Clock Skew:</td>
<td>-0.364</td>
</tr>
<tr>
<td class="label">Setup Relationship:</td>
<td>0.317</td>
</tr>
<tr>
<td class="label">Logic Level:</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay:</td><td> cell: 0.000, 0.000%; route: 0.363, 100.000%</td></tr>
<tr>
<td class="label">Arrival Data Path Delay:</td><td> cell: 1.099, 43.657%; route: 0.960, 38.136%; tC2Q: 0.458, 18.207%</td></tr>
<tr>
<td class="label">Required Clock Path Delay:</td><td> cell: 0.000, 0.000%; route: 0.363, 100.000%</td></tr>
</table>
<br/>
<h3>Path&nbsp2</h3>
<b>Path Summary:</b></br>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-2.993</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>42.926</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>39.933</td>
</tr>
<tr>
<td class="label">From</td>
<td>spi_u0/spi_dor_0_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>spi_u0/spi_shift_o_0_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>spi_clk_inter[R]</td>
</tr>
</table>
<b>Data Arrival Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>39.683</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>40.046</td>
<td>0.363</td>
<td>tCL</td>
<td>RR</td>
<td>1271</td>
<td>u_div_5/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>40.409</td>
<td>0.363</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>spi_u0/spi_dor_0_s0/CLK</td>
</tr>
<tr>
<td>40.867</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>1</td>
<td>spi_u0/spi_dor_0_s0/Q</td>
</tr>
<tr>
<td>41.347</td>
<td>0.480</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>spi_u0/n111_s1/I1</td>
</tr>
<tr>
<td>42.446</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>spi_u0/n111_s1/F</td>
</tr>
<tr>
<td>42.926</td>
<td>0.480</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>spi_u0/spi_shift_o_0_s0/D</td>
</tr>
</table>
<b>Data Required Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>spi_clk_inter</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>21</td>
<td>spi_u0/spi_clk_inter_s1/F</td>
</tr>
<tr>
<td>40.363</td>
<td>0.363</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>spi_u0/spi_shift_o_0_s0/CLK</td>
</tr>
<tr>
<td>40.333</td>
<td>-0.030</td>
<td>tUnc</td>
<td> </td>
<td> </td>
<td>spi_u0/spi_shift_o_0_s0</td>
</tr>
<tr>
<td>39.933</td>
<td>-0.400</td>
<td>tSu</td>
<td> </td>
<td>1</td>
<td>spi_u0/spi_shift_o_0_s0</td>
</tr>
</table>
<b>Path Statistics:</b>
<table class="summary_table">
<tr>
<td class="label">Clock Skew:</td>
<td>-0.364</td>
</tr>
<tr>
<td class="label">Setup Relationship:</td>
<td>0.317</td>
</tr>
<tr>
<td class="label">Logic Level:</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay:</td><td> cell: 0.000, 0.000%; route: 0.363, 100.000%</td></tr>
<tr>
<td class="label">Arrival Data Path Delay:</td><td> cell: 1.099, 43.657%; route: 0.960, 38.136%; tC2Q: 0.458, 18.207%</td></tr>
<tr>
<td class="label">Required Clock Path Delay:</td><td> cell: 0.000, 0.000%; route: 0.363, 100.000%</td></tr>
</table>
<br/>
<h3>Path&nbsp3</h3>
<b>Path Summary:</b></br>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-2.993</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>42.926</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>39.933</td>
</tr>
<tr>
<td class="label">From</td>
<td>spi_u0/spi_dor_1_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>spi_u0/spi_shift_o_1_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>spi_clk_inter[R]</td>
</tr>
</table>
<b>Data Arrival Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>39.683</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>40.046</td>
<td>0.363</td>
<td>tCL</td>
<td>RR</td>
<td>1271</td>
<td>u_div_5/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>40.409</td>
<td>0.363</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>spi_u0/spi_dor_1_s0/CLK</td>
</tr>
<tr>
<td>40.867</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>1</td>
<td>spi_u0/spi_dor_1_s0/Q</td>
</tr>
<tr>
<td>41.347</td>
<td>0.480</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>spi_u0/n110_s0/I1</td>
</tr>
<tr>
<td>42.446</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>spi_u0/n110_s0/F</td>
</tr>
<tr>
<td>42.926</td>
<td>0.480</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>spi_u0/spi_shift_o_1_s0/D</td>
</tr>
</table>
<b>Data Required Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>spi_clk_inter</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>21</td>
<td>spi_u0/spi_clk_inter_s1/F</td>
</tr>
<tr>
<td>40.363</td>
<td>0.363</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>spi_u0/spi_shift_o_1_s0/CLK</td>
</tr>
<tr>
<td>40.333</td>
<td>-0.030</td>
<td>tUnc</td>
<td> </td>
<td> </td>
<td>spi_u0/spi_shift_o_1_s0</td>
</tr>
<tr>
<td>39.933</td>
<td>-0.400</td>
<td>tSu</td>
<td> </td>
<td>1</td>
<td>spi_u0/spi_shift_o_1_s0</td>
</tr>
</table>
<b>Path Statistics:</b>
<table class="summary_table">
<tr>
<td class="label">Clock Skew:</td>
<td>-0.364</td>
</tr>
<tr>
<td class="label">Setup Relationship:</td>
<td>0.317</td>
</tr>
<tr>
<td class="label">Logic Level:</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay:</td><td> cell: 0.000, 0.000%; route: 0.363, 100.000%</td></tr>
<tr>
<td class="label">Arrival Data Path Delay:</td><td> cell: 1.099, 43.657%; route: 0.960, 38.136%; tC2Q: 0.458, 18.207%</td></tr>
<tr>
<td class="label">Required Clock Path Delay:</td><td> cell: 0.000, 0.000%; route: 0.363, 100.000%</td></tr>
</table>
<br/>
<h3>Path&nbsp4</h3>
<b>Path Summary:</b></br>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-2.993</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>42.926</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>39.933</td>
</tr>
<tr>
<td class="label">From</td>
<td>spi_u0/spi_dor_2_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>spi_u0/spi_shift_o_2_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>spi_clk_inter[R]</td>
</tr>
</table>
<b>Data Arrival Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>39.683</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>40.046</td>
<td>0.363</td>
<td>tCL</td>
<td>RR</td>
<td>1271</td>
<td>u_div_5/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>40.409</td>
<td>0.363</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>spi_u0/spi_dor_2_s0/CLK</td>
</tr>
<tr>
<td>40.867</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>1</td>
<td>spi_u0/spi_dor_2_s0/Q</td>
</tr>
<tr>
<td>41.347</td>
<td>0.480</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>spi_u0/n109_s0/I1</td>
</tr>
<tr>
<td>42.446</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>spi_u0/n109_s0/F</td>
</tr>
<tr>
<td>42.926</td>
<td>0.480</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>spi_u0/spi_shift_o_2_s0/D</td>
</tr>
</table>
<b>Data Required Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>spi_clk_inter</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>21</td>
<td>spi_u0/spi_clk_inter_s1/F</td>
</tr>
<tr>
<td>40.363</td>
<td>0.363</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>spi_u0/spi_shift_o_2_s0/CLK</td>
</tr>
<tr>
<td>40.333</td>
<td>-0.030</td>
<td>tUnc</td>
<td> </td>
<td> </td>
<td>spi_u0/spi_shift_o_2_s0</td>
</tr>
<tr>
<td>39.933</td>
<td>-0.400</td>
<td>tSu</td>
<td> </td>
<td>1</td>
<td>spi_u0/spi_shift_o_2_s0</td>
</tr>
</table>
<b>Path Statistics:</b>
<table class="summary_table">
<tr>
<td class="label">Clock Skew:</td>
<td>-0.364</td>
</tr>
<tr>
<td class="label">Setup Relationship:</td>
<td>0.317</td>
</tr>
<tr>
<td class="label">Logic Level:</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay:</td><td> cell: 0.000, 0.000%; route: 0.363, 100.000%</td></tr>
<tr>
<td class="label">Arrival Data Path Delay:</td><td> cell: 1.099, 43.657%; route: 0.960, 38.136%; tC2Q: 0.458, 18.207%</td></tr>
<tr>
<td class="label">Required Clock Path Delay:</td><td> cell: 0.000, 0.000%; route: 0.363, 100.000%</td></tr>
</table>
<br/>
<h3>Path&nbsp5</h3>
<b>Path Summary:</b></br>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-2.993</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>42.926</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>39.933</td>
</tr>
<tr>
<td class="label">From</td>
<td>spi_u0/spi_dor_3_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>spi_u0/spi_shift_o_3_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>spi_clk_inter[R]</td>
</tr>
</table>
<b>Data Arrival Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>39.683</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>40.046</td>
<td>0.363</td>
<td>tCL</td>
<td>RR</td>
<td>1271</td>
<td>u_div_5/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>40.409</td>
<td>0.363</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>spi_u0/spi_dor_3_s0/CLK</td>
</tr>
<tr>
<td>40.867</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>1</td>
<td>spi_u0/spi_dor_3_s0/Q</td>
</tr>
<tr>
<td>41.347</td>
<td>0.480</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>spi_u0/n108_s0/I1</td>
</tr>
<tr>
<td>42.446</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>spi_u0/n108_s0/F</td>
</tr>
<tr>
<td>42.926</td>
<td>0.480</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>spi_u0/spi_shift_o_3_s0/D</td>
</tr>
</table>
<b>Data Required Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>spi_clk_inter</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>21</td>
<td>spi_u0/spi_clk_inter_s1/F</td>
</tr>
<tr>
<td>40.363</td>
<td>0.363</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>spi_u0/spi_shift_o_3_s0/CLK</td>
</tr>
<tr>
<td>40.333</td>
<td>-0.030</td>
<td>tUnc</td>
<td> </td>
<td> </td>
<td>spi_u0/spi_shift_o_3_s0</td>
</tr>
<tr>
<td>39.933</td>
<td>-0.400</td>
<td>tSu</td>
<td> </td>
<td>1</td>
<td>spi_u0/spi_shift_o_3_s0</td>
</tr>
</table>
<b>Path Statistics:</b>
<table class="summary_table">
<tr>
<td class="label">Clock Skew:</td>
<td>-0.364</td>
</tr>
<tr>
<td class="label">Setup Relationship:</td>
<td>0.317</td>
</tr>
<tr>
<td class="label">Logic Level:</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay:</td><td> cell: 0.000, 0.000%; route: 0.363, 100.000%</td></tr>
<tr>
<td class="label">Arrival Data Path Delay:</td><td> cell: 1.099, 43.657%; route: 0.960, 38.136%; tC2Q: 0.458, 18.207%</td></tr>
<tr>
<td class="label">Required Clock Path Delay:</td><td> cell: 0.000, 0.000%; route: 0.363, 100.000%</td></tr>
</table>
<br/>
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